1. Field of the Invention
The present invention relates to a computer-aided timing adjusting method and apparatus for correcting timing errors (set-up errors and hold errors) by automatically or semiautomatically adjusting the timing of a logic circuit whose layout has been designed, and a storage medium stored with a program for executing this method.
2. Description of the Related Art
In logic circuit, in accordance with its development in integration and with the miniaturizing of its element, a ratio of wiring propagation delay time to gate propagation delay time has been becoming increasingly greater. Therefore, timing analysis for the logic circuit whose layout has been designed is performed with computer.
In the prior art timing adjusting, the designer refers to the gate propagation delay time and wiring propagation delay time of a timing error path, selects a cell to be replaced or a position to be inserted, and performs replacing the cell or inserting a cell.
But, since a signal dull value or a number of error paths in a case where a plurality of timing error paths are overlapped is not taken into consideration, it is difficult to perform timing adjusting effectively.
Also, by replacing or inserting a cell, since the gate propagation delay time and wiring propagation delay time of the cells around it change, timing analysis must be performed again after the net list and layout are renewed to confirm the adjusting result. In repetition of such a processing, since replacing and inserting of cells are manually performed by the designer, timing adjusting takes a long time.
Accordingly, an object according to the present invention is to provide a computer-aided timing adjusting method and apparatus, and a storage medium stored with a program to execute the method, wherein the timing adjusting is more effectively performed, whereby the adjusting time will be shortened.
In the 1st aspect of the present invention, there is provided a computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the method comprising the steps of, as shown in FIGS. 4A through 4C for example,: preparing a timing error information including the types of timing errors and timing error paths, a delay information relating to signal propagation delay, and a logic information including function and driving capability of each cell in the combinational circuits; when the timing error information has one that the sequential circuit is a set-up error path: selecting a cell which is estimated with referring to the delay information to be the greatest cause for the set-up error arising; searching a cell whose function is the same as the selected cell and driving capability is larger than the selected cell; and replacing the selected cell with the searched cell.
With the 1st aspect according to the present invention, since the ratio of the decreasing amount of path delay time to the increasing amount of the driving capability becomes relatively greater, whereby it will be effective and the timing adjusting time will be shortened.
In the 2nd aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, wherein, in the preparing step, the delay information has input signal dull values of the cells, wherein, in the selecting step, as shown in FIGS. 4A through 4C for example, a cell in the proceeding stage of a cell with the largest input signal dull value is selected.
In the 3rd aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, wherein, in the preparing step, as shown in FIGS. 15A through 15C for example, the delay information has output-wiring propagation delay times, wherein, in the selecting step, a cell whose output-wiring propagation delay time is the maximum is selected.
In the 4th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, wherein, in the preparing step, the delay information has gate propagation delay times, wherein, in the selecting step, as shown in FIGS. 16A through 16C for example, the cell in the proceeding stage of a cell whose propagation delay time is the maximum is selected.
In the 5th aspect of the present invention, there is provided a computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the sequential circuits having first and second sequential circuits whose combinational circuits have a common part, the method comprising the steps of, as shown in FIGS. 6A and 6B for example,: preparing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in the combinational circuits; when the timing error information has one that the first and second sequential circuits each are timing error paths: judging whether or not the types of the timing errors of the timing error paths are the same; and if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in the common part with a cell, in the logic information, with the same function and a different driving capability, or inserting a cell in the logic information into the common part without changing the function of the common part.
With the 5th aspect according to the present invention, since the timings in the same type and plurality of timing error paths are simultaneously and effectively adjusted, the timing adjusting time will be shortened.
In the 6th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 5th aspect, wherein, as shown in FIGS. 6A and 6B for example, if the type of the timing errors is a set-up error, then the replacing or inserting step comprises the steps of: selecting a cell in the common part; searching, in the logic information, a cell having the same function as and a greater driving capability than the selected cell; and replacing the selected cell with the searched cell.
In the 7th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 6th aspect, wherein, in the selecting step, as shown in FIGS. 6A and 6B for example, if a plurality of the second sequential circuits exist, then a cell, in the common part, with the largest number of set-up error paths is selected.
In the 8th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 5th aspect, wherein the replacing or inserting step, as shown in FIGS. 11A and 11B for example, if the type of the timing errors is a hold error, then comprises the steps of: selecting a cell in the common part; and inserting a cell, in the logic information, before or after the selected cell so as not to change the function as before insertion.
In the 9th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 8th aspect, wherein, in the selecting step, as shown in FIGS. 11A and 11B for example, if a plurality of the second sequential circuits exist, then a cell, in the common part, with the largest number of hold error paths is selected.
In the 10th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in any one of the 6th through 9th aspects, wherein, as shown in FIGS. 7A and 7B or FIGS. 8A and 8B for example, when a plurality of cells are selected in the selecting step, if the common part is on the downstream side of the circuit between the first and second flip-flops, then the cell on the most downstream side is selected, and if the common part is on the upstream side, then the cell on the most upstream side is selected.
With the 10th aspect according to the present invention, since the propagation delay time mainly and only at the common part changes, the timings of a multi set-up error path will be more effectively and simultaneously adjusted.
In the 11th aspect of the present invention, there is provided a computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the sequential circuits having first and second sequential circuits whose combinational circuits have a common part, the method comprising the steps of, as shown in FIGS. 9A and 9B for example,: preparing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in the combinational circuits; when the timing error information has one that the first and second sequential circuits each are timing error paths: judging whether or not the types of the timing errors of the timing error paths are the same; and if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in the combinational circuit of the first sequential circuit and not in the common part with a cell, with the same function and a different driving capability, or inserting a cell in the logic information into the common part without changing the function of the common part.
With the 11th aspect according to the present invention, since the timing of mainly and only a targeted timing error path is adjusted, the timing of a complicated multi timing error path will be effectively adjusted.
In the 12th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 11th aspect, wherein, as shown in FIGS. 9A and 9B for example, if the first and second sequential circuits are a set-up error path and a hold error path, respectively, then the replacing or inserting step comprises the steps of: selecting a cell which is in the set-up error path and not in the common part; searching a cell, in the logic information, having the same function as and a greater driving capability than the selected cell; and replacing the selected cell with the searched cell.
In the 13th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 11th aspect, wherein, as shown in FIGS. 9A and 9B for example, if the first sequential circuit is a set-up error path, a plurality of the second sequential circuits exist, and at least one of the second sequential circuits is a hold error path, then the replacing or inserting step comprises the steps of: selecting a cell which is in the set-up error path and has the smallest number of hold error paths; searching a cell, in the logic information, having the same function as and a greater driving capability than the selected cell; and replacing the selected cell with the searched cell.
In the 14th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 11th aspect, wherein, as shown in FIGS. 14A and 14B for example, in the replacing or inserting step, if the first and second sequential circuits are a hold error path and a set-up error path, respectively, then a cell is inserted into a part which is in the hold error path and not in the common part so as not to change the function as before insertion.
In the 15th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 11th aspect, wherein, as shown in FIGS. 14A and 14B for example, if the first sequential circuit is a hold error path, a plurality of the second sequential circuits exist, and at least one of the second sequential circuits is a set-up error path, then the replacing or inserting step comprises the steps of: selecting a cell which is in the hold error path and has the smallest number of set-up error paths; and inserting a cell, in the logic information, before or after the selected cell.
In the 16th aspect of the present invention, there is provided a computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the sequential circuits having first and second sequential circuits whose combinational circuits have a common part, the method comprising the steps of, as shown in FIGS. 18A and 18B for example,: preparing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in the combinational circuits; when the timing error information has one that the first and second sequential circuits each are timing error paths: judging whether or not the types of the timing errors of the timing error paths are the same; and if the types are different, then: counting the number of set-up error paths and the number of hold error paths for each cell in the first sequential circuit; selecting a cell based on the counted number in accordance with a rule of a priority order; and in order to lower the degree of the timing errors, replacing the selected cell with a cell, in the logic information, with the same function and a different driving capability, or inserting a cell, in the logic information, before or after the selected cell so as not to change the function as before insertion.
With the 16th aspect according to the present invention, by providing a priority order for cell selection, the cell to be replaced or the cell insertion position will be narrowed to one, whereby effective adjusting will be performed.
In the 17th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 16th aspect, wherein, as shown in FIGS. 18A and 18B for example, when the first sequential circuit is a set-up error path, the replacing or inserting step comprises the steps of: searching a cell, in the logic information, having the same function as and a greater driving capability than the selected cell; and replacing the selected cell with the searched cell.
In the 18th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 17th aspect, wherein, as shown in FIG. 17 for example, the rule is such that the larger the number of set-up error paths, the higher the priority order, and that, if the number of the set-up error paths are equal, the smaller the number of hold error paths, the higher the priority order.
In the 19th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 17th aspect, wherein, as shown in FIG. 17 for example, in the preparing step, a delay information having the input signal dull value of each cell in the combination circuits is further prepared, wherein the rule is such that a cell in the proceeding stage of a cell with the largest input signal dull value is selected, that, if a plurality of cells are selected thereby, then the larger the number of set-up error paths, the higher the priority order, and that, if the number of the set-up error paths are equal, then the smaller the number of hold error paths, the higher the priority order.
In the 20th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 16th aspect, wherein, as shown in FIGS. 20A and 20B for example, in the replacing or inserting step, when the first sequential circuit is a hold error path, a cell is inserted before or after the selected cell so as not to change the function as before insertion.
In the 21st aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 20th aspect, wherein, as shown in FIGS. 20A and 20B for example, the rule is such that the smaller the number of set-up error paths, the higher the priority order, and that, if the number of the set-up error paths are equal, the larger the number of hold error paths, the higher the priority order.
In the 22nd aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st, 6th, 12th, 13th or 17th aspect, wherein, in the logic information, cells are classified into families, each of the families having the same function and the same number of input and output, wherein, in the searching step, a cell is searched in the same family as the selected cell.
In the 23rd aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 5th, 11th or 16th aspect, wherein, as shown in FIGS. 24A through 24D for example, in the preparing step, the timing error information includes hold shortage time at each hold error path, the delay information includes signal propagation delay time of each cell and wiring-between adjacent cells in the combinational circuits, and the logic information includes basic delay time of each cell, the basic delay time being propagation delay time of cell itself under a predetermined condition, wherein, in the inserting step, cells, the sum of the basic delay times of which is equal to or larger than the hold shortage time, are selected and inserted.
In the 24th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 23rd aspect, wherein, as shown in FIGS. 27A through 27D for example, in the inserting step, candidates of cells, in the logic information, to be inserted are narrowed manually, and a cell to be inserted is automatically selected.
With the 24th aspect according to the present invention, excessive adjusting will be prevented more securely.
In the 25th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st, 5th, 11th or 16th aspect, as shown in FIG. 2 for example, further comprising a step of setting a lower limit before adjusting timing errors, wherein, in the preparing step, the timing error information includes shortage time which is set-up shortage time or hold shortage time; wherein, in the replacing or inserting step, the replacing or inserting is performed only for timing error path whose shortage time is larger than the lower limit.
With the 25th aspect according to the present invention, even if the shortage time is smaller than the lower limit and the timing error path is excluded from an object of direct adjusting, since adjusting for the timing error is indirectly performed, it will be corrected. Thus, excessive adjusting will be prevented, and the adjusting time will be shortened.
In the 26th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, as shown in FIGS. 21A through 21D for example, further comprising a step of calculating signal propagation delay time of adjusted set-up error path, wherein the selecting, searching, replacing, and calculating steps are repeatedly executed until the set-up error is corrected.
With the 26th aspect according to the present invention, every time of replacing, cell to be replaced will be effectively selected.
In the 27th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, as shown in FIGS. 22A through 22D for example, further comprising a step of calculating signal propagation delay time of adjusted set-up error path, wherein the searching, replacing, and calculating steps are repeatedly executed until the set-up error is corrected.
With the 27th aspect according to the present invention, the number of cells to be replaced will be less than in the case of the 26th aspect, whereby influence on non-adjusted paths will be reduced.
In the 28th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 5th, 11th or 16th aspect, as shown in FIGS. 21A through 21D or FIGS. 22A through 22D for example, further comprising a step of calculating signal propagation delay time of adjusted timing error path, wherein the replacing or inserting, and calculating steps are repeatedly executed until the timing error is corrected.
In the 29th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 1st aspect, as shown in FIG. 23 for example, further comprising the steps of: detecting timing errors in the semiconductor integrated circuit after the replacing step; and renewing the timing error information and the delay information; wherein the selecting, searching, replacing, detecting and renewing steps are repeatedly executed until all the set-up errors are corrected.
With the 29th aspect according to the present invention, timing adjusting is repeatedly performed full-automatically.
In the 30th aspect of the present invention, there is provided a computer-aided timing adjusting method as defined in the 5th, 11th or 16th aspect, as shown in FIG. 23 for example, further comprising the steps of: detecting timing errors in the semiconductor integrated circuit after the replacing or inserting step; and renewing the timing error information; wherein the selecting, searching, replacing or inserting, detecting and renewing steps are repeatedly executed until all the timing errors are corrected.
In the 31st aspect of the present invention, there is provided a storage medium stored with a program for executing a computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the method comprising the steps of: preparing a timing error information including the types of timing errors and timing error paths, a delay information relating to signal propagation delay, and a logic information including function and driving capability of each cell in the combinational circuits; when the timing error information has one that the sequential circuit is a set-up error path: selecting a cell which is estimated with referring to the delay information to be the greatest cause for the set-up error arising; searching a cell whose function is the same as the selected cell and driving capability is larger than the selected cell; and replacing the selected cell with the searched cell.
In the 32nd aspect of the present invention, there is provided a computer-aided timing adjusting apparatus for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the apparatus comprising: a storage device for storing a timing error information including the types of timing errors and timing error paths, a delay information relating to signal propagation delay, and a logic information including function and driving capability of each cell in the combinational circuits; and a computer for executing the steps of: when the timing error information has one that the sequential circuit is a set-up error path: selecting a cell which is estimated with referring to the delay information to be the greatest cause for the set-up error arising; searching a cell whose function is the same as the selected cell and driving capability is larger than the selected cell; and replacing the selected cell with the searched cell.
With the 32nd aspect according to the present invention, since the ratio of the decreasing amount of path delay time to the increasing amount of the driving capability becomes relatively greater, whereby it will be effective and the timing adjusting time will be shortened.
In the 33rd aspect of the present invention, there is provided a computer-aided timing adjusting apparatus for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the sequential circuits having first and second sequential circuits whose combinational circuits have a common part, the apparatus comprising: a storage device for storing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in the combinational circuits; a computer for executing the steps of: when the timing error information has one that the first and second sequential circuits each are timing error paths: judging whether or not the types of the timing errors of the timing error paths are the same; and if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in the common part with a cell, in the logic information, with the same function and a different driving capability, or inserting a cell in the logic information into the common part without changing the function of the common part.
With the 33rd aspect according to the present invention, since the timings in the same type and plurality of timing error paths are simultaneously and effectively adjusted, the timing adjusting time will be shortened.
In the 34th aspect of the present invention, there is provided a computer-aided timing adjusting apparatus for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the sequential circuits having first and second sequential circuits whose combinational circuits have a common part, the apparatus comprising: a storage device for storing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in the combinational circuits; a computer for executing the steps of: when the timing error information has one that the first and second sequential circuits each are timing error paths: judging whether or not the types of the timing errors of the timing error paths are the same; and if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in the combinational circuit of the first sequential circuit and not in the common part with a cell, with the same function and a different driving capability, or inserting a cell in the logic information into the common part without changing the function of the common part.
With the 34th aspect according to the present invention, since the timing of mainly and only a targeted timing error path is adjusted, the timing of a complicated multi timing error path will be effectively adjusted.
In the 35th aspect of the present invention, there is provided a computer-aided timing adjusting apparatus for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, the semiconductor integrated circuit including sequential circuits, each of the sequential circuits having first and second flip-flops and a combinational circuit connected between an output of the first flip-flop and the input of the second flip-flop, the first and second flip-flops operating in synchronization with a clock, the sequential circuits having first and second sequential circuits whose combinational circuits have a common part, the apparatus comprising: a storage device for storing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in the combinational circuits; a computer for executing the steps of: when the timing error information has one that the first and second sequential circuits each are timing error paths: judging whether or not the types of the timing errors of the timing error paths are the same; and if the types are different, then: counting the number of set-up error paths and the number of hold error paths for each cell in the first sequential circuit; selecting a cell based on the counted number in accordance with a rule of a priority order; and in order to lower the degree of the timing errors, replacing the selected cell with a cell, in the logic information, with the same function and a different driving capability, or inserting a cell, in the logic information, before or after the selected cell so as not to change the function as before insertion.
With the 35th aspect according to the present invention, by providing a priority order for cell selection, the cell to be replaced or the cell insertion position will be narrowed to one, whereby effective adjusting will be performed.